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SX1210
ADVANCED COMMUNICATIONS & SENSING
5. Data Processing
5.1. Overview
5.1.1. Block Diagram
Figure 19, illustrates the SX1210 data processing circuit. Its role is to interface the data from the demodulator and
the uC access points (SPI, IRQ and DATA pins). It also controls all the configuration registers.
The circuit contains several control blocks which are described in the following paragraphs.
Rx
SX1210
DATA
CONTROL
IRQ_0
IRQ_1
Data
Rx
SYNC
SPI
Tx
RECOG.
PACKET
HANDLER
FIFO
(+SR)
CONFIG
DATA
NSS_DATA
SCK
MOSI
MISO
Figure 19: SX1210’s Data Processing Conceptual View
The SX1210 implements several data operation modes, each with their own data path through the data processing
section. Depending on the data operation mode selected, some control blocks are active whilst others remain
disabled.
5.1.2. Data Operation Modes
The SX1210 has three different data operation modes selectable by the user:
Continuous mode : each bit received is accessed in real time at the DATA pin. This mode may be used if
adequate external signal processing is available.
Buffered mode : each byte received is stored in a FIFO and accessed via the SPI bus. uC processing overhead
is hence significantly reduced compared to Continuous mode operation. The packet length is unlimited.
Packet mode (recommended) : user only retrieves payload bytes to/from the FIFO. Sync word is automatically
detected and stripped off while optional CRC check and DC free data decoding can be performed. The uC
processing overhead is hence reduced further compared to Buffered mode. The maximum payload length is
limited to the maximum FIFO limit of 64 bytes
Rev 2– Sept 8 , 2008
th
Page 28 of 73
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